[rescue] sun 3/60 update

Thu May 29 10:46:04 EDT 2025

Le jeu. 29 mai 2025 à 15:04, Romain Dolbeau <romain at dolbeau.org> a écrit :
> In any case, it means all
> of that logic would need to be understood and rewritten to change from
> select-by-RAS to select-by-CAS :-(

Might not be that bad; the current logic seems a bit complex, but it's
just because PAL language is terrible.
See below for a rough automatic translation from EQN to Verilog.

Basically, the current logic, if we ignore TWOWAY and SEL0/SEL1 is
* use A[2..21] (20 bits) to access a set of 1 MiB SIMM, so a block of 4 MiB
* use A0/A1/SIZ0/SIZ1 (as per the 68k bus specifications) to pick
bytes, and use the 4 RAS signal to enable/disable them
* use A[22..27] to pick which set of SIMM to actually use through the
CAS signals.
(TWOWAY just semantically swap A2 and A22).

That last bullet imply you could use 256 MiB (2^6 * 4 MiB), but the
upper three bits (A25-A27) are only used to disable the CAS, and A24
is only used 2/3 - so you really get only 6 * 4 MiB, for 24MiB total.
There's no hardware to support smaller/larger SIMM that I can see.

So assuming a similar restriction of "fixed size SIMM", it should be
possible to hardwire for e.g. 16 MiB 72-pins SIMMs by similar logic:

* use A[2..23] (22 bits) to access a single 16 MiB SIMM, so a block of 16 MiB
* use A0/A1/SIZ0/SIZ1 to pick bytes, and use the 4 CAS signal to
enable/disable them (CAS not RAS here!)
* use A[22..27] to pick which set of SIMM to actually use through one
RAS signal per SIMM
(and then maybe support TWOWAY again to interleave pair of SIMMs)

Essentially the same logic as now, but swapping the populated/address
check with the bus-sizing check for CAS and RAS. It should be possible
to get 16 (one simm) to 64 MiB of RAM (four simm) that way, provided
the PROM can be fixed to report it (or even more, but that would
require a lot of SIMMs or the use of larger, less common SIMMs).

Of course the real problem would be that the refresh logic might also
need updating...

The current RAS logic:

module PAL16L8_x1578-01 (
    input    i_SIZ0,
    input    i_SIZ1,
    input    i_A0,
    input    i_A1,
    input    i_SEL0n,
    input    i_SEL1,
    input    i_WRITEn,
    input    i_R_ACKn,
    input    i_M_PDn,
    output    o_RE13n,
    output    o_RE12n,
    output    o_RE11n,
    output    o_RE10n,
    output    o_RE03n,
    output    o_RE02n,
    output    o_RE01n,
    output    o_RE00n
);
    assign o_RE00n    = (~i_M_PDn) ? (i_R_ACKn & (i_SEL0n | ~i_WRITEn)
& (~i_A0 | ~i_A1 | i_SEL0n) & (~i_SIZ1 | ~i_A1 | i_SEL0n) & (i_SIZ1 |
i_SIZ0 | i_SEL0n) & (~i_SIZ1 | ~i_SIZ0 | ~i_A0 | i_SEL0n)) : 'bZ;
    assign o_RE01n    = (~i_M_PDn) ? (i_R_ACKn & (i_SEL0n | ~i_WRITEn)
& (i_A0 | ~i_A1 | i_SEL0n) & (~i_SIZ1 | ~i_A0 | i_A1 | i_SEL0n) &
(i_SIZ1 | i_SIZ0 | i_A1 | i_SEL0n) & (~i_SIZ1 | ~i_SIZ0 | i_A1 |
i_SEL0n)) : 'bZ;
    assign o_RE02n    = (~i_M_PDn) ? (i_R_ACKn & (i_SEL0n | ~i_WRITEn)
& (~i_A0 | i_A1 | i_SEL0n) & (i_SIZ0 | i_A1 | i_SEL0n) & (~i_SIZ1 |
i_A1 | i_SEL0n)) : 'bZ;
    assign o_RE03n    = (~i_M_PDn) ? (i_R_ACKn & (i_SEL0n | ~i_WRITEn)
& (i_A0 | i_A1 | i_SEL0n)) : 'bZ;
    assign o_RE10n    = (~i_M_PDn) ? (i_R_ACKn & (~i_SEL1 | ~i_WRITEn)
& (~i_A0 | ~i_A1 | ~i_SEL1) & (~i_SIZ1 | ~i_A1 | ~i_SEL1) & (i_SIZ1 |
i_SIZ0 | ~i_SEL1) & (~i_SIZ1 | ~i_SIZ0 | ~i_A0 | ~i_SEL1)) : 'bZ;
    assign o_RE11n    = (~i_M_PDn) ? (i_R_ACKn & (~i_SEL1 | ~i_WRITEn)
& (i_A0 | ~i_A1 | ~i_SEL1) & (~i_SIZ1 | ~i_A0 | i_A1 | ~i_SEL1) &
(i_SIZ1 | i_SIZ0 | i_A1 | ~i_SEL1) & (~i_SIZ1 | ~i_SIZ0 | i_A1 |
~i_SEL1)) : 'bZ;
    assign o_RE12n    = (~i_M_PDn) ? (i_R_ACKn & (~i_SEL1 | ~i_WRITEn)
& (~i_A0 | i_A1 | ~i_SEL1) & (i_SIZ0 | i_A1 | ~i_SEL1) & (~i_SIZ1 |
i_A1 | ~i_SEL1)) : 'bZ;
    assign o_RE13n    = (~i_M_PDn) ? (i_R_ACKn & (~i_SEL1 | ~i_WRITEn)
& (i_A0 | i_A1 | ~i_SEL1)) : 'bZ;
endmodule // PAL16L8_x1578-01

The current CAS logic (I think S0n...S5n is just whether a bank of 4
SIMMs is populated)

module PAL20L8_x1585-01 (
    input    i_M_S0n,
    input    i_M_S1n,
    input    i_M_S2n,
    input    i_M_S3n,
    input    i_M_S4n,
    input    i_M_S5n,
    input    i_PA02_22,
    input    i_PA23,
    input    i_PA24,
    input    i_PA25,
    input    i_PA26,
    input    i_PA27,
    input    i_M_ACKn,
    output    o_CEn,
    output    o_TWOWAYn,
    output    o_CAS5n,
    output    o_CAS4n,
    output    o_CA3n,
    output    o_CAS2n,
    output    o_CAS1n,
    output    o_CAS0n,
    input    i_M_PDn
);
    assign o_CAS0n    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S0n | i_PA02_22
| i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
    assign o_CAS1n    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S1n | ~i_PA02_22
| i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
    assign o_CAS2n    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S2n | i_PA02_22
| ~i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
    assign o_CA3n    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S3n | ~i_PA02_22
| ~i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
    assign o_CAS4n    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S4n | i_PA02_22
| i_PA23 | ~i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
    assign o_CAS5n    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S5n | ~i_PA02_22
| i_PA23 | ~i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
    assign o_TWOWAYn    = (~i_M_PDn) ? ((i_M_S1n | i_M_S0n | i_M_S2n |
i_M_S3n | i_M_S4n | i_M_S5n) & (i_M_S1n | i_M_S0n | i_M_S2n | i_M_S3n
| ~i_M_S4n | ~i_M_S5n) & (i_M_S1n | i_M_S0n | ~i_M_S2n | ~i_M_S3n |
~i_M_S4n | ~i_M_S5n)) : 'bZ;
    assign o_CEn    = (~i_M_PDn) ? (i_M_ACKn & (i_M_S0n | i_PA02_22 |
i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27) & (i_M_S1n | ~i_PA02_22 |
i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27) & (i_M_S4n | i_PA02_22 |
i_PA23 | ~i_PA24 | i_PA25 | i_PA26 | i_PA27) & (i_M_S5n | ~i_PA02_22 |
i_PA23 | ~i_PA24 | i_PA25 | i_PA26 | i_PA27) & (i_M_S2n | i_PA02_22 |
~i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27) & (i_M_S3n | ~i_PA02_22 |
~i_PA23 | i_PA24 | i_PA25 | i_PA26 | i_PA27)) : 'bZ;
endmodule // PAL20L8_x1585-01

-- 
Romain Dolbeau