[rescue] sun 3/60 update

[Romain Dolbeau]

Le sam. 24 mai 2025 à 05:51, Dan Moisa via rescue <rescue at sunhelp.org> a écrit :
> You guys are right about the 72 pin SIMMS - they are 32 bits instead of 8, so that's a x4 reduction right there without messing with the address line decoding, and so on.
> They just took 4 8bit and smashed it together, they even have 4 CAS/RAS pairs and parity, which is brilliant. Proof is right here:

Just read the relevant JEDEC standard (JEDEC Standard No. 21–C Page
4.4.2–1), and I suspect "look" is the operative word here :-( (that
JEDEC standard is available from the website for free, but you need to
register and be logged in).

The various /RE[0-3] signals (for RAS) have assigned pins, but from
the table "CONFIGURATION PIN ASSIGNMENT TABLE", it seems they are not
always connected on the module itself. For instance, the small and
common 4 MiB module has A9/A11/A10 on pins 19/29/32, and is NC on pins
33/34/45 - those labelled /RE1, /RE2, /RE3. The 16 MiB module has A12
on pin 33 but is otherwise the same.

I'm not sure what it really means, but my understanding is that all 4
bytes are meant to use the same RAS signal, and the additional RAS are
only used when using 2 banks (instead of using an extra address bit,
as normally address bits are used twice for row and column and
therefore quadruple the capacity, dual-rank only doubles it). I
suppose byte selection is done by selecting the per-byte CAS signal in
this case (this is supported by the documentation for the modern
IS41LV16105D DRAM device saying "Byte Write and Byte Read operation
via two CAS"). However, the 3/60 memory controller does the selection
on the RAS signals instead. The CAS is the same for everyone per the
schematic (or rather, there's four of them, but they are all generated
from the same input through U908, so are always identical)

So I suspect replacing the four 30-pins sockets by a single 72-pins
socket is not as easy as it could be :-( This would impact the wiring
of U907A (single shared input instead of 4), U908A (four inputs
instead of a shared one), and the much more complex job of reworking
the U800 and U802 PAL ; U800 generates the 8 RE (for two banks of 4
SIMMs, then shared between the three set of two banks), while U802
generates six CAS, one for each bank of four simms. I believe it
should be one RE per bank (so 6 of them), and then one CAS per byte
(so just 4). Or twelve RE if the current scheme of two-per-bank is
kept.

I'm not sure why the 3/60 needs two sets of RE for each pair; as far
as I can tell, they are the same but discriminated based on input
signals SEL0- and SEL1. Those come from U801, and have two possible
sources based on signal TWOWAY-: either A2 (for both) or hardwiring of
GND and VCC... which set both to enabled ?!? (SEL0- is active-low,
SEL1 is active-high). And TWOWAY- happens to be generated by U802
alongside the CAS signals... My best guess is that if both sets of 4
SIMMs are filled (or empty) in all pairs (three pairs in total), then
the memory is interleaved at the word level, and consecutive accesses
can be a bit faster (always accessing a different set of DRAMs), so
you want to fill out SIMMs in set of 8 rather than 4 for performance
reason. Was that a known thing for the 3/60? In any case, it means all
of that logic would need to be understood and rewritten to change from
select-by-RAS to select-by-CAS :-(

Cordially,

-- 
Romain Dolbeau