[rescue] sun 3/60 update

[Romain Dolbeau]

Le mar. 3 juin 2025 à 06:01, Dan Moisa via rescue <rescue at sunhelp.org> a écrit :
> It would be good to give names to the U114 state machine too, specifically C.S3

I have looked at it, and actually they are aptly named!

TL;DR: they become active during the state labelled S3/S5/S* in
Motorola's timing schematics for bus cycles.

The 74F145 captures its inputs on a rising clock edge, and /CLR
(Labelled as /Mr in the schematics) is a reset and clears all
registers to 0.
The way U114 is wired:
* With AS inactive, U114 is in clear mode and all the C.S* are deactivated
* With AS active, at each rising clock of CLK- (so negative edge of
the CPU clock):
=> C.S3 captures 1 (its input is wired to Vcc)
=> C.S5 captures C.S3
=> C.S7 captures C.S5
=> C.S9 captures C.S7
Si they activate on successive negative edges of the CPU clock
following the activation of AS. They are reset to 0 at the end of the
bus cycle when AS is deactivated.
>From Moto's timing diagrams for the MC68020 (Figure 10-13 in the UM),
AS is activated 3 to 25ns after a negative edge (characteristic #9 @
20 MHz) between what is called S0 and S1, so C.S3 activates upon entry
in S3.

> What's the formula for the refresh cycle, is it size dependent? with internal counter refresh, I would expect that as long as you get to all locations within the RAM spec, it wouldn't matter. I'll try putting in 4MB sticks and see if they still act like reliable 1MB ones.

Refresh cycles are time-dependent and are specified per-chip (and
there were different standards...), and are indirectly size-dependent.
In RBD mode, you only need to have enough refresh cycles in a given
time period to cover all rows. For a chip with a 15 milliseconds
window (don't have the reference handy, but that's the value I
remember for 1 MiB DRAM chip), doing a cycle every 12.8 microseconds
is enough to cover 1024 rows in time, so fine for 1 MiB. For larger
chips, you get more rows (2048 for a 4 MiB), so either the chip can be
refreshed less often (longer window), or the frequency of refresh
cycles must be increased.

> I'll take a look at your CPLD pull request. If all the pins are there, I can put it on a TQFP to through-hole adapter and wire it up to some sockets to mimic the original chips,

In the PLD file I did not arrange the pin list in any specific order,
I just wanted to be able to check the file in WinCUPL. You can have
them in any order you want on the I/O pins to make the PCB routing
easier.
If you do create an adapter, it would be a good idea for it to have
some way of powering it up independently and a JTAG header for
programming the CPLD. Also beware the CPLD might have specific
decoupling requirements.

Cordially,

-- 
Romain Dolbeau