[rescue] rescue Digest, Vol 214, Issue 7

Chase Rayfield cusbrar2 at yahoo.com
Fri Sep 18 21:41:06 CDT 2020


I'm interested in building an sbus card like this also, and have been thinking
on it for awhile with no progress! Also it might be possible to make a crypto
accelerator interface so native applications with an updated SSL could work
without a proxy like bodge. It would be nice for instance to have a modern
accelerated SSL to drop into the last version of Opera that just knows to talk
to the accelerator.

I have a copy of the book but no floppies unfortunately or the SERFBoard.

A better lead might be the people that made the SPERT-II and TetraSPERT.
Perhaps someone even has the VHDL/Verilog code they wrote for their FPGA... to
interface with sbus. They were using a small 6k gate / 250 cell Xilinx 4006
FPGA... If they still happen to have the files they would be compatible with
Xilinx XACT (pre Xilinx ISE, I don't think there is a free version of it so
you'd have to have a hard dongle or unix FlexLM license but the code might be
readable at least).


Microchip ATF-15 or AT40k might be ideal for doing the level conversion the
3.3v ATF-15 chips appear to be tolerant of up to 7 volts and is cheap as
chips, and sbus itself is should be happy to be driven by a 3.3v device which
would then be easy to interface with a modern part like an ECP-5G or ICE40
etc... which now have open source toolchains too.

Must be careful of the sbus card power limit of 10W when trying to do so much
with it so it may be wise to use switch mode regulation so less power is lost
there. If you add a USB port you are already down to 1.5Amps @ 5V so 7.5W.
This also means using as many ASICs as possible and as little FPGA power as
possible you'll still need an IO FPGA + a modestly beefy management FPGA.

So to summarize my thoughts and wishlist, ATF-15 IO and bus handling FPGA, +
ECP-5 with a small 1 or 2 RISC-V core DVI-D + AUDIO + USB + 1x PCIe + MUX to
NVMe with SCSI emulation for NVMe and USB. Keyboard and mouse support. It
should be possible to support ethernet via USB for people that don't have
ethernet cards, or perhaps to allow the board to hit the bus less for SSL
acceleration, Maybe 1x RISC-V MAIX M1 board to handle acceleration tasks.

Maybe another board that is an ATF-15 + ice40 Ultra + as many RISCV MAIX M1
boards talking to one of the fast serial ports on the ice40 as will fit
(probably 8) which would put 16 RISC-V fairly fast coresB  in the SS to be
used for general acceleration like for SSL etc, each of these boards can also
do 1TOP of interger AI operations so that'd be as much as 8 teraops to play
with in a transputer style fasion. Might be possible to hang an ethernet chip
off the other side of the ice40... hmm. I'm better at the electrical side of
things than the logic design side, but most of what I do is in the
microcontroller space.

I think at some point someone will make a RISC-V GPU ASIC for embedded Vulkan
etc... I think another advantage of relying on asics as much as possible also
is ease of implementation and leaving FPGAs to do what they do best, glue

It might be possible to put an RPI on a com module on an sbus board... but eh,
not a huge fan of that.

Another consideration is making the board 64bit sbus capable for use in the
early Ultras... with best performance.

Anyway I'd enjoy hearing your thoughts on the matter also! As long as the IO
interface is figured out this would open the path for others also to make neat
stuff for sparcstations, maybe even emulations of old rare complex boards like
the AG10e (which I do have). A board like that would make NetBSD and Solaris
for instance much more pleasant for many.

Chase Rayfield

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