[rescue] sparc10 cpu - what to do.

Jonathan Patschke jp at celestrion.net
Sun Dec 18 13:02:20 CST 2016

On Sun, 18 Dec 2016, Patrick Giagnocavo wrote:

> Isn't the Itanium the second or third time that Intel tried VLIW or
> VLIW like architectures?


> iAPX 432, up to 321 bits in length instructions
> i860 with program-accessible pipelines

Yep, but in the i860's case, that was probably an afterthought because of
how poorly i860 handled pipeline flushes.

> My view: VLIW CPUs represent the ultimate in vendor lockin, given the
> complexity of the compilers needed.

Pretty fair analysis, and it's not just due to the scale of complexity
with regards to code generation: the specificity is such that neither the
chip vendor nor the compiler writer can be very creative in subsequent
iterations without ruining the performance of existing hardware or

Although the same coupling argument could be made for RISC, at least RISC
tends to (with some major exceptions like ARM and PA-RISC) make
compiler-writing mechanical to such a degree that it approaches boring.

Jonathan Patschke
Austin, TX

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