[rescue] rescue Digest, Vol 129, Issue 16
michael.99.thompson at gmail.com
Tue Aug 27 19:00:18 CDT 2013
> Date: Mon, 26 Aug 2013 21:00:49 -0700
> From: "r.stricklin" <bear at typewritten.org>
> Subject: Re: [rescue] rescue Digest, Vol 129, Issue 15
> On Aug 26, 2013, at 6:14 PM, Michael Thompson wrote:
> > The A & C rows of the J2 and the B row of the J3 was used for a
> > CPU<->Memory bus, or a graphics bus.
> > I think that the pinout of the memory bus differed between the
> Yes. This bus is "optimized for DRAM timing", which could potentially
> memory-mapped framebuffers.
> The pinout of the bus was at least the same enough for memory boards to
> interoperate between sun3, sun3x, and SPARC VME CPUs.
> If it matters, I am specifically interested in its use on sun2. But I'll
> anything. I have a sun2 memory board that I want a clearer understanding
> in order to troubleshoot its failure mode more effectively.
You have a 2/75?
The schematic for the 2/120 Multibus backplane is here:
The memory board is here:
That shows the signals for the DRAM bus and may be close to the 3/75 bus.
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