[rescue] rescue Digest, Vol 129, Issue 15
bear at typewritten.org
Tue Aug 27 13:56:13 CDT 2013
> On Aug 26, 2013, at 6:14 PM, Michael Thompson wrote:
>> The A & C rows of the J2 and the B row of the J3 was used for a
>> CPU<->Memory bus, or a graphics bus.
>> I think that the pinout of the memory bus differed between the processors.
> If it matters, I am specifically interested in its use on sun2. But I'll
take anything. I have a sun2 memory board that I want a clearer understanding
of, in order to troubleshoot its failure mode more effectively.
BTW here is the draft of what I am working on. Obviously, you can get some
sense for what is going on with just what I've been able to reverse engineer
here. Having the P2 bus connector pinouts would make it practically
transparent. They have to be SOMEWHERE...!
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