[rescue] rescue Digest, Vol 129, Issue 15
bear at typewritten.org
Mon Aug 26 23:00:49 CDT 2013
On Aug 26, 2013, at 6:14 PM, Michael Thompson wrote:
> The A & C rows of the J2 and the B row of the J3 was used for a
> CPU<->Memory bus, or a graphics bus.
> I think that the pinout of the memory bus differed between the processors.
Yes. This bus is "optimized for DRAM timing", which could potentially include
The pinout of the bus was at least the same enough for memory boards to
interoperate between sun3, sun3x, and SPARC VME CPUs.
If it matters, I am specifically interested in its use on sun2. But I'll take
anything. I have a sun2 memory board that I want a clearer understanding of,
in order to troubleshoot its failure mode more effectively.
until further notice
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