[rescue] FS/FTGH: Sun kit

Richard legalize at xmission.com
Tue Jan 17 00:32:27 CST 2006

In article <200601170546.AAA12421 at Sparkle.Rodents.Montreal.QC.CA>,
    der Mouse <mouse at Rodents.Montreal.QC.CA>  writes:

> > Umm.... just because something has registers labelled X, Y, and Z is
> > no reason to infer that it has a "transform engine", if by that term
> > you mean the ability to apply 4x4 coordinate matrices to points.
> I believe the cg6's "transform engine" is an engine for transforming
> (X,Y,Z) three-space coordinates into (X,Y) screen coordinates.

Why do you believe this?

> I do
> not know whether it is capable of doing perspective transformations (as
> opposed to being restricted to parallel projection).

...or maybe its not capable of projection at all.

> Strictly speaking, I do not know even that much about it, but the
> conjecture is fairly strong.
> > For instance, the pixel processor chip in Evans & Sutherland's ESV
> > workstation (a machine from 1989, so its comparable technology to the
> > cg6) has low-level commands that accept X, Y, and Z triplets for
> > rasterization of lines and points.  However, there is no transform
> > engine in the pixel processor chip -- its just a rasterizer.
> Well, call it a rasterizer, if you prefer; what you describe here is a
> fairly close match to what I think the cg6 has - or rather, the cg6's
> "transform engine" is, I think, *part* of what you're calling a
> rasterizer; specifically, the part that converts (X,Y,Z) in three-space
> to (X,Y) in screen coordinates.

Nope.  A rasterizer interpolates between endpoints.  The X,Y,Z values
on the ESV pixel processor chip are used to interpolate values for the
screen position and depth in the Z-buffer.  This is why I say that
presence of a Z register doesn't imply that there is a transformation
engine present, particularly since you're saying that the cg6 is
woefully underdocumented.

However, I find it funny that they would spend the money necessary for
the RAM to contain a Z buffer but would skimp on the RAM to contain
the color buffer.  Single color buffers instead of double color
buffers are the usual way that a hardware manufacturer would save on
RAM costs in a graphics accelerator supporting 3D graphics.

It is highly likely that the Z register might control something like
the window id buffer in the ESV -- using window planes was a common
strategy for accelerating 2D updates in frame buffers of the period.
"The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ:
             Pilgrimage: Utah's annual demoparty

More information about the rescue mailing list