[rescue] USparc q: out of order EXECUTION vs. DISPATCH

Patrick Giagnocavo patrick at mail.zill.net
Thu Jun 9 23:07:00 CDT 2005

In reading through a Sun publication:

The Sun Enterprise 3500 - 6500 Server Family: Architecture and Implementation 

It seems that the USII chips mentioned can do out of order execution, but not o-o-o dispatch:

"Out-of-order completion permits the intefer and branch units to
execute other instructions while a long-latency instruction

"UltraSPARC does not make use of the similarly-named but much more
complex strategy called out-of-order dispatch.  In the US,
instructions are always dispatched in the order they appear in the
instruction stream.  Some processors attempt to dynamically reorder
the instruction stream in an attempt to more fully optimize
superscalar pipelines.  The US architecture design team opten not to
implement this feature in order to keep the processor deisgn simple
enough to run at high clock rates."

Q:  what processors DO have ooo dispatch?

second Q: if I run 2-way RAM interleave on an E4000, will I see a
performance increase ? This is what I was trying to find out when I
came across this doc via Google.


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