[rescue] SS5 mobo
mcguire at neurotica.com
Tue Mar 2 15:08:41 CST 2004
On Mar 2, 2004, at 4:04 PM, Janet L. Campbell wrote:
>> I must be misremembering the internal architecture of the SS5 then,
>> and if that's the case, I stand corrected. Does the operating system
>> not "see" an Mbus from its perspective on an SS5? (I don't have one
>> handy at the moment)
> No, there's no Mbus visible at all.
> The microSparc and TurboSparc CPUs incorporate the IU, FPU, SRMMU,
> level cache, memory controller and Sbus controller all onto one chip.
> The TurboSparc also has a second level cache external to the chip.
> Nearly everything that attaches to the CPU hooks in through either the
> memory bus (RAM, the AFX slot) or the Sbus
> The SuperSparc and HyperSparc CPUs have the memory controller and Mbus
> Sbus interface on the mainboard, not on the CPU modules. The Mbus was
> needed as an abstraction layer to allow multiple CPU transactions to be
> handled cleanly and to deal with cache coherence.
I'm misremembering then, probably getting it mixed up with the
SS10/SS20 architecture. Thanks for the info. It's been a while. :-)
> The microSparc/TurboSparc memory access latency is a lot lower because
> overhead of the Mbus glue isn't there. Memory transactions also don't
> have to fight for bus space with Sbus transactions, so they can be
> immediately. This gave the SS4/SS5 the lowest memory latency of any
Was this a latency/bandwidth tradeoff?
> -Janet [just another hardware hacker]
You rock. :-)
Dave McGuire "My tummy hurts now, but my soul
Cape Coral, FL feels a little better." -Ed
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