[rescue] IBM :: Different
george at webbastard.org
Wed Feb 13 08:57:10 CST 2002
On Wednesday 13 February 2002 04:13 am, you wrote:
> On Wed, 13 Feb 2002, Jonathan C. Patschke wrote:
> > > The way POWER4 systems are organized is that they have two cores on
> > > each chip. Each core has 512kB/512kB level 1 cache. The module has an
> > > 8MB (or is it 10MB?) level 2 cache for both cores, and the processor
> > > board (with two POWER4's) has 128MB level 3 cache.
> > Uhm. Damn. They don't screw around, do they? I have servers with less
> > memory than that.
> > So, is main memory optional? Can you just bootstrap the kernel into the
> > cache? :)
> Hehehe. These machines have a minimum configuration of 2GB RAM, if memory
> serves. And they can connect into an RS/6000 SP switch for future
Yes, but remember, for IBM Mainframes compared to everyone else, this is like
having a 2 or 4 processor server with 512K or 1 meg cache each, with 8 megs
of unified L2 cache for the processors and 128 megs of buffer RAM between the
Proc and a 2GB main RAM. (no doubt all kickass fast...)
IBM always has to be different. Remember the Stretch?
or the 360/90? (the vaporware machine that got them sued by Control Data)
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